Modern digital signal processors (DSP) face multiple challenges. DSPs often execute software that includes nested loops, which include an inner loop and one or more outer loops. In order to improve performance of a DSP, certain instructions may be executed in a pipelined fashion, in which multiple instructions are executed at the same time by different functional units of the DSP. However, executing nested loops in a pipelined fashion introduces difficulties in determining whether to execute an instruction associated with the one or more outer loops, for example determining a predicate for the instruction in an efficient manner.